1. Field of the Invention
The present invention relates to a split gate type nonvolatile semiconductor memory device, and a method of fabricating the same, and more particularly, to a split gate type nonvolatile semiconductor memory device using a self-alignment approach to overcome misalignment of a control gate, and a method of fabricating the same.
2. Description of the Related Art
The applications for nonvolatile semiconductor memory devices have been increasing in various fields such as mobile communication systems, memory cards and the like, since it can electrically erase and store and retain data even when power is not applied. Among nonvolatile semiconductor memories, a flash memory can program in a unit of cell and erase in a unit of block or sector. The flash memory is classified into a Metal-Nitride-Oxide-Silicon (MNOS) memory using nitride, and a floating gate memory using a floating gate, depending on the type of charge storage used in the device. Typically, a floating gate type nonvolatile semiconductor memory can be classified into a stack gate type nonvolatile semiconductor memory, a split gate type nonvolatile semiconductor memory or a combination thereof.
A conventional split gate type nonvolatile semiconductor memory device has a source region formed by implanting impurity ions into an active region of a semiconductor substrate. A pair of floating gates are disposed adjacent to each other on the semiconductor substrate at both sides of the source region while sharing the source region, and a gate insulating layer is interposed between the floating gate and the substrate. An inter-gate insulating layer having a relatively high thickness is formed on a surface of the floating gate between the floating gate and a control gate. A tunneling insulating layer is formed at a sidewall of the floating gates opposite to the source region. The control gate extends toward the inter-gate insulating layer to be overlapped with the floating gate. The control gate also extends from a sidewall of the floating gate by a predetermined length toward the semiconductor substrate having the gate insulating layer. A drain region is disposed in the semiconductor substrate down of the sidewall of the control gate.
The above described split gate type memory device can be fabricated in the following method, for example. First, after a gate insulating layer, a first polysilicon layer for forming the floating gate, and a nitride layer are subsequently formed, a nitride pattern is formed using a photolithography process to expose a portion of the first polysilicon layer to be formed as the floating gate. Next, the first polysilicon layer is thermally oxidized to form the inter-gate insulating layer, and the nitride pattern is removed. After that, the first polysilicon layer, which is not oxidized, is etched using the inter-gate insulating layer as an etching mask to form the floating gate.
Next, an insulating layer for a tunneling insulating layer and a second polysilicon layer for a control gate are formed using a Chemical Vapor Deposition (CVD) method on an entire surface of the semiconductor substrate having the inter-gate insulating layer. After that, the photolithography process is used to pattern the second polysilicon layer and the insulating layer, thereby forming the control gate and the tunneling insulating layer. Next, impurity ions are implanted into the semiconductor substrate between the floating gates to form the source region, and impurity ions are implanted into the semiconductor substrate at an outer side of the control gate to form the drain region. After that, a source line and a bit line are formed to complete the split gate type nonvolatile semiconductor memory device. An example of the conventional split gate type nonvolatile semiconductor memory device is disclosed in U.S. Pat. No. 6,646,923, incorporated herein by reference.
However, in a method of fabricating the conventional split gate type nonvolatile semiconductor memory device, the photolithography process is used to form the control gate. However, the photolithography process can cause misalignment, thereby causing an overlap variation. If misalignment occurs, an effective channel length under the control gate can be different between the memory cells, and a difference in characteristics between adjacent cells, that is, an odd cell and an even cell having mirror symmetry, can result. In the effective channel length of the control gate, this variation causes a variation of a threshold voltage of the memory cell. The variation of the threshold voltage between the odd cell and the even cell causes a difference between the cells in ON current, thereby degrading the uniformity of the memory cell.
Accordingly, a technique is required to overcome a misalignment drawback in the photolithography process for forming the control gate.